The present invention relates generally to integrated circuit metallization, and more particularly to a method of planarizing copper wiring.
In the field of integrated circuit manufacturing, it is well known that significant density advantages result from forming planar metallization patterns (where the xe2x80x9cmetallization patternsxe2x80x9d interconnect one or more transistors, capacitors, resistors, and other semicondutor electronic components formed on a wafer). One of the significant trends in the industry is to produce such planar metallization patterns using so-called xe2x80x9cchemical-mechanical polishxe2x80x9d (or xe2x80x9cchem-mech polishxe2x80x9d or xe2x80x9cCMPxe2x80x9d) techniques. In CMP, the frontside of the wafer is held against a rotating polish wheel, and a chemical slurry is introduced that facilitates the removal of one or more metal layers on the wafer through a combination of chemical reaction and physical abrasion. See for example U.S. Pat. No. 4,944,836, issued Jul. 31, 1990 to Beyer et al. and assigned to the assignee of the present invention (a CMP method of planarizing metal relative to surrounding passivation, or planarizing passivation relative to metallurgy).
In addition to the general advantages afforded by CMP, particular density advantages result from forming an integrated metallurgy in pre-planarized passivation. That is, as shown in U.S. Pat. No. 4,789,648, issued Dec. 6, 1988 to Chow et al and assigned to the assignee of the present invention (hereinafter the xe2x80x9cChow patentxe2x80x9d), integrated metallurgy (that is, a single layer of metal that includes both a vertical portion that extends down to underlaying layers on a wafer to contact conductive structures formed thereon, and horizontal portions that provide electrical interconnection) can be formed by depositing and defining apertures through two passivation layers that are planarized by CMP, then depositing metal over the entire structure and polishing away portions of the metal that extend above the planarized passivation layers. Normally, the horizontal and vertical portions of the metallurgy are formed using two layers of metal; the Chow patent maximizes conductivity by eliminating the interlayer interface that normally exists between the horizontal and vertical portions of the metallurgy structure.
In the prior art, it is well known to utilize aluminum alloys or tungsten as the metallurgy for integrated circuits. However, the conductivity characteristics of these materials may not be sufficient as the minimum on-chip dimensions decrease below 0.25 um. These metallurgies are typically deposited on the wafer utilizing chemical vapor deposition and other deposition techniques. As interconnect dimensions are reduced the aspect ratio (that is, the ratio of height relative to width) of vias, or openings, formed through interlevel dielectrics increases, leading to voids in metals deposited utilizing directional techniques. In addition, at smaller geometries metal lines become more susceptible to electromigration-induced faults. Thus, a recent development in the art has been the development of copper metallurgies. Copper has low resistivity, high electromigration resistance, and can be deposited by electroplating techniques that greatly reduce void formation. However, because copper is a soft metal without a highly protective native oxide, and cannot be easily patterned using standard reactive ion etching techniques, it presents unique challenges, particularly in the area of CMP. Various slurries for CMP of copper (and/or barrier materials for copper) have been proposed in the prior art. These techniques include the following:
1) nitric acid, a polymer, a surfactant, and sulfuric or sulfonic acid for removing copper from printed circuit boards in a non-CMP process (U.S. Pat. No. 4,632,727, to Nelson and assigned to Psi Star);
2) iron-amononia-EDTA (U.S. Pat. No. 4,954,142, to Patrick, et al. and assigned to the assignee of the present invention);
3) water, a solid abrasive, and one of HNO3, H2SO4, and AgNO3 (U.S. Pat. No. 5,225,034 and divisonal 5,534,490 to Yu et al. and assigned to Micron Technology);
4) an oxidizing agent and a silica abrasive, the slurry having a pH between 2 and 4, to polish tungsten, copper, titanium nitride, or tungsten silicide (U.S. Pat. No. 5,340,370 and divisional 5,516,346, to Cadien et al. and assigned to Intel);
5) ammonium persulfate/KOH with a pH of 10 (xe2x80x9cAlkaline Formulation for Chemical Mechanical Polishing of Copper Utilizing Azole Passivationxe2x80x9d, IBM Technical Disclosure Bulletin, Vol. 37, No. 10, October 1994 Pg. 187));
6) silica or alumina grains, aminoacetic acid, and hydrogen peroxide (European Patent Application 94119785.7, published Jun. 28, 1995, based on JP 313406/93);
7) colloidal silica, sodium chlorite, and deionized water (U.S. Pat. No. 5,451,55 1, issued Sep. 5, 1995 to Krishnan et al.);
8) an oxidizing agent, a surfactant, and deionized water, with a uniform dispersion of alumina particulates that have an aggregate size distribution of less than about one micron and an average diameter less than approximately 0.4 microns (U.S. Pat. No. 5,527,423, issued Jun. 18, 1996 to Neville et al and assigned to Cabot Inc.);
9) ferric nitrate, BTA, poly(ethylene glycol) and alumina particulates (xe2x80x9cChemical-Mechanical Polishing of Copper In Acidic Media,xe2x80x9d Luo et al., 1996 CMP-MIC Conference, Feb. 22-23, 1996, pp. 145-51);
10) use of alumina particulates in a first CMP slurry to polish the bulk metal (tungsten or copper), followed by use of silica particulates in a second CMP slurry to polish an underlayer of Ti/TiN (U.S. Pat. No. 5,676,587, issued Oct. 14, 1997 to Landers et al. and assigned to the assignee of the present invention); and
11) Silica, glycine, and BTA (U.S. Pat. No. 5,770,095 to Sasaki et al., and assigned to Toshiba Corp.).
In general, the prior art set forth above deals with polishing of copper (in some cases with barrier materials) in conventional metal line or stud via applications. However, when polishing metal as shown in the Chow patent, particular challenges are presented that must be addressed in the CMP process.
In the invention, copper is removed by CMP in a slurry that comprises an oxidizer, an oxidation inhibitor, and an additive that appreciably regulates copper complexing with the oxidation inhibitor, resulting in a high removal rate of copper without appreciable removal of the underlying metallic and dielectric layers or copper corrosion, and with minimal loss of copper in patterned interconnects.